For professionals in PCB design, procurement, hardware engineering, and process engineering, the concept of HDI "tiers" (or "orders") is often confusing in daily work: What exactly are 1st-tier, 2nd-tier, and 3rd-tier HDI? Does a higher layer count automatically mean a higher tier? How can you quickly distinguish between them by looking at blueprints or cross-sections?
The "sub-channel" architecture in DDR5 was introduced to address a challenge that arises as data rates increase: how to maintain high memory bandwidth without making the access granularity excessively coarse.
Higher resolution exposes PCB layout errors more starkly: 12-bit designs require "caution," 16-bit designs demand "absolute precision," and in 24-bit designs, even the slightest layout oversight will manifest in the data. This article covers LSB size, six fundamental design principles, ground plane management, the thermocouple effect, and nine real-world examples of poor PCB layout—serving as a pr
When working with RS-485 communication, many hardware engineers encounter a question that appears simple but is actually a potential pitfall: is isolation truly necessary for RS-485? Some argue that isolation is required for distances exceeding a few dozen meters, while others contend that it is mandatory in industrial environments. So, what is the actual deciding factor for whether RS-485 require
At its most fundamental level, a DRAM storage cell consists of just one transistor and one capacitor (1T1C). Given such a simple structure, how is it possible to store tens of gigabytes—or even more—of data? Furthermore, the electrical charge stored within a DRAM cell is not permanent; it leaks over time, can be disturbed during read operations, and requires constant refreshing. Therefore, to trul
