DDR Architecture Design: 01. DDR5 Channel and Sub-channel Structure
The "sub-channel" architecture in DDR5 was introduced to address a challenge that arises as data rates increase: how to maintain high memory bandwidth without making the access granularity excessively coarse.01. What is a Channel?
A channel is a data path between a memory controller and a set of DRAM chips. It comprises a complete suite of signals, including data lines (DQ), data strobes (DQS), command/address (CA) lines, clock signals, control signals, power, and reference signals.In traditional DDR, a single memory channel has a data width of 64 bits. This 64-bit figure represents the number of data bits transmitted in parallel across the data bus during a single transfer. For instance, when a desktop platform is described as having "dual-channel" memory, it means the CPU's memory controller possesses two independent 64-bit data channels, effectively doubling the theoretical bandwidth.
In essence, a channel is a comprehensive set of communication resources between the controller and the DRAM—it is far more than just a few DQ lines.
02. The 64-bit Channel in DDR4
A DDR4 DIMM data channel is 64 bits wide. On a non-ECC UDIMM, this channel consists of 64 data lines; for server modules equipped with ECC, additional bits are included for error correction. When the controller initiates an access to this 64-bit channel, data is transmitted continuously in a "burst" format.DDR4 typically uses a Burst Length (BL) of 8 (BL8). In a single burst, each DQ line transmits 8 consecutive data units. Consequently, a single BL8 transfer across a 64-bit DDR4 channel yields:
64 bits × BL8 = 512 bits = 64 bytes.
Since 64 bytes matches the size of a standard CPU cache line, the combination of a 64-bit channel and BL8 in DDR4 is naturally well-suited for transferring a single 64-byte cache line in one operation.
However, as we move to DDR5, data rates continue to climb. If the same design philosophy were applied—maintaining a 64-bit channel while scaling up to, say, a Burst Length of 16 (BL16)—a problem arises: a single transfer would suddenly balloon to 128 bytes. For many types of memory access, this granularity is simply too coarse—much like trying to buy a single bottle of water, only for the shopkeeper to say, "Sorry, we only sell by the case." It’s not necessarily that you can’t afford it; it’s just that the whole situation feels a bit off.
03. DDR5 2×32-bit Sub-channels
DDR5 employs two independent 32-bit sub-channels. A core motivation for this design is to maintain a reasonable data access granularity even when using a Burst Length (BL) of 16 (BL16).In DDR5, the Burst Length has been increased to BL16. If the data path were a single, unified 64-bit channel, a single transfer would amount to:
64 bits × BL16 = 1024 bits = 128 bytes
For certain scenarios, this is too large. It results in overly coarse access granularity, which can lead to wasted bandwidth and reduced flexibility in controller scheduling. DDR5 addresses this by taking a different approach: logically splitting the 64-bit channel into two 32-bit sub-channels. Consequently, the data volume for a single sub-channel with BL16 becomes:
32 bits × BL16 = 512 bits = 64 bytes
By extending the burst length while simultaneously subdividing the channel, DDR5 ensures that each access—via a single sub-channel—maintains a data granularity of 64 bytes.
This balances high data rates with efficient access; otherwise, the gains from higher speeds would be undermined by the inefficiencies of an excessively coarse burst granularity.
04. Sub-channels, BL16, and Prefetch
To understand DDR5 sub-channels, one must consider them in the context of BL16 and prefetch mechanisms. The changes in DDR5 represent a cohesive set of adjustments rather than an isolated modification.DDR4 typically utilizes an 8n prefetch, a Burst Length of 8 (BL8), and a 64-bit channel. In contrast, DDR5 employs a 16n prefetch, a Burst Length of 16 (BL16), and two 32-bit sub-channels. On the surface, it may appear that various parameters are simply being "doubled" or "halved," but the underlying logic is to maintain a balance between access granularity and bandwidth efficiency.
Therefore, one should not interpret a "sub-channel" as DDR5 "cutting the number of data lines in half." A more accurate perspective is that DDR5 employs a more granular channel organization—combined with longer bursts and higher data rates—to enhance overall efficiency.
